1. Field of the Invention
The present invention relates to a control system with multiprocessor architecture for an internal combustion powertrain.
2. Description of Related Art
Known powertrains comprise a control system that is capable of supervising the operation of the entire powertrain and comprises a single-processor computing unit having just one processor. In the great majority of cases, a powertrain manufacturer purchases the control system from an external supplier and requests said supplier to ensure that it is possible to implement control functions in the control system, which functions are intended for electronic devices produced by the powertrain manufacturer.
Typically, the producer of the control system tends to oversize the computing capacity and interconnectivity capacity of the computing unit in order to allow the engineers of the powertrain manufacturer to use the computing unit to implement control functions which they have developed themselves. However, the above-described solution of oversizing the computing capacity of a single-processor computing unit often proves inadequate in that execution of the control functions developed by the engineers of the powertrain manufacturer may interfere negatively with the execution of the powertrain control developed by the producer of the control system. Moreover, increasing the computing capacity of a single-processor computing unit can be achieved by modifying the internal architecture of the processor or by increasing the operating frequency of the processor itself; however, modifying the internal architecture of the processor is extremely costly, while increasing the operating frequency of the processor can complicate data exchange by means of existing buses that are designed to operate at a specific operating frequency.
U.S. Pat. No. 5,367,665 A1 (issued Nov. 22, 1994) discloses a multi-processor system for a motor vehicle and having at least two processors; the system carries out a first sequence of steps when power is switched on and, for a restart during operation, executes a second sequence of steps (the system distinguishes between power on and a restart and selects, the corresponding step sequence). In addition, a check is provided as to whether the number of resets of a processor has exceeded a pregiven threshold; in this case, a processor is transferred into the standby state for the operating cycle, which is then running.
U.S. Pat. No. 5,454,095 A1 (issued Sep. 26, 1995) discloses a multi-processor system, which has at least two processors jointly accessing the same memory and is useful for controlling processes of motor vehicles. The system memory is divided into at least two sectors, so as a first processor accesses one memory sector only in the read mode and a second processor accesses it only in the write mode; the second processor accesses the other memory sector only in the read mode and the first processor accesses it only in the write mode. The processors are synchronized in such a way that the processors access the memory in the same way at the same time.